It is generally known that, in inverter devices of the above-mentioned type, an equivalent output capacitance C.sub.OSS exists between the drain and the source of the MOS transistor. This output capacitance is a parasitic capacitance produced when the transistor is manufactured, and is the main cause of a power drop occurring during a high-frequency operation.
Namely, an electric current which charges and discharges the output capacitance flows at each switching of the MOS transistor and is consumed by the on-state resistance of the transistor, whereby the loss increases in proportion to the frequency.
Furthermore, a maximum electric power that can be input to the inverter is restricted by the peak value of a voltage applied to the source and drain of the transistor during operation. That is, the input power is limited to less than the maximum rated voltage of the transistor.